The present invention relates to a technology for designing a semiconductor integrated circuit device, and in particular to a computer-readable storage medium that is preferable for optimization with respect to the reliability of designing logic products by a cell unit, using delay libraries having parameters to calculate degradation by hot carriers, and a technology that is effective to application of a method for designing a semiconductor integrated circuit device.
In prior arts, in designing semiconductor integrated circuit devices, the design has been automated and saved manpower by using computer software called CAD (Computer-Aided Design) and DA (Design Automation). The design of electric characteristics of logic circuits that constitute a semiconductor integrated circuit device has been optimized by verifying the operations of circuits that man developed, through simulation by using a CAD tool, which is called xe2x80x9cCircuit Simulationxe2x80x9d. The electric characteristics to be optimized herein are mainly physical quantities directly pertaining to the performance of a semiconductor integrated circuit device such as delay time and power consumption, etc. But, in line with the recent progress of semiconductor integrated circuit devices, reliability design has been required with respect to the aged changes (that is, service life) of the semiconductor integrated circuit devices. As one of the representative examples of physical phenomenon regarding the service life of the semiconductor integrated circuit devices, characteristic degradation due to hot carriers may be listed.
A description is given of degradation due to the hot carriers with reference to FIG. 35 that is a view showing a saturation mode (Vds greater than Vdsat) in which an MOSFET transistor operates and FIG. 36 that is a characteristic view showing a decrease in a drain current. In line with the shrinking of a device dimension, the lateral field of channel area A of an NMOSFET device of FIG. 35 has gradually become higher and higher. By an increase in the lateral field, the channel electrons will acquire energy, and becomes so-called xe2x80x9chot electronsxe2x80x9d. These higher electrons can be injected into a gate oxide film or can cause impact ionization which produces electron-hole pairs, of which the electrons can also be injected into the gate oxide film. Electrons can also break bonds at the Sixe2x80x94SiO2interface, causing a possibility that the interface is impaired. In all these cases, if electrons become trapped in the oxide film or if electrons fill the interface states, drain current Ids decreases with respect to the drain voltage Vds as in FIG. 36, and device performance may be degraded.
Therefore, as technologies for designing semiconductor integrated circuit devices in which characteristic degradation due to hot carriers is taken into consideration, there are, for example, the literature of IEDM Technical Digest December, 1998, pp. 93 through 96, xe2x80x9cRatio Based Hot-Carrier Degradation Modeling for Aged Timing Simulation of Millions of Transistor Digital Circuitsxe2x80x9d, U.S. Pat. No. 5,974,247, and Japanese Patent Laid-Open No. 135388/1999, and Japanese Patent Laid-Open No. 219380/1999.
In test literatures and publications, technologies pertaining to:
(a) A method for calculating degradation due to hot carriers in delay library levels;
(b) A method for calculating degradation due to hot carriers in library cell propagation delay on the basis of input signal transition time, and output signal transition time/load oriented to output-attached capacity; and
(c) A method for calculating (b) based on a fluctuation in a power supply voltage and operating temperature are described.
However, the inventor examined the technologies disclosed in the above-described document and patent application publications, and the following was made clear. That is, in the technologies described in the above document and patent application publications,
(1) Delay library/calculation is done for one degradation table entry with respect to only one circuit operation time,
(2) Delay library/calculation is done only one time (one combination of duties and frequencies) with respect to one degradation table entry, and
(3) Delay libraries and hot carrier libraries are separate from each other.
These are listed as problematic points.
Therefore, with respect to the above-described (1) through (3), the inventor takes the following into consideration:
(1xe2x80x2) Parameters that describe the time dependence of degradation are contained in a delay library, and a single library necessary to describe the degradation with respect to different circuit operation times is determined,
(2xe2x80x2) Parameters that describe the time dependence of degradation are contained in a delay library, and a single library necessary to describe the degradation in an optional combination of duties and frequencies, and
(3xe2x80x2) Delay libraries and hot carrier libraries are merged into one library.
Thereby, if there is only one library per technology, the system does not require the repetition of the hot carrier degradation in terms of the circuit level with respect to different circuit operation frequencies.
Also, the design system and design flow, in which the reliability is taken, for optimizing the reliability and performance, which were enabled by the above-described literature and patent publications, are as shown in, for example, FIG. 37. In the design method, it is necessary to cross a time-consuming detailed simulation part 10 (that takes much time) and the whole-production simulation part 20 when performing the optimization of the design. The entire design optimization must be carried out by crossing the whole-product simulation part 20 to the time-consuming detailed simulation part 10 (that takes much time). That is, in the technologies described in the literature and patent application publications, it becomes necessary to re-produce the libraries where a design change (27a) occurs in line with topology, frequencies, signal paths, and circuit operating times, excepting the design change (27b) with respect to the power supply source and temperature.
It is therefore an object of the invention to provide a storage medium having adequate parameters in the design of semiconductor integrated circuit devices.
It is another object of the invention to provide a design technology of semiconductor integrated circuit devices that, when performing optimization of the design by using degradation information of parameters Ac and n, does not require crossing a time-consuming detailed simulation part (that takes much time) and the whole-product simulation part and is able to perform the design optimization in the whole-product simulation part in a design method for taking reliability in the design and optimizing the reliability and performance.
The above-described and other objects and novel features of the invention will be made more apparent through the description in the specification hereof and the accompanying drawings.
The representative factors of the inventive points of the present application are briefly described below.
That is, a computer-readable storage medium according to the invention includes, as delay libraries of various types of logic cells that constitute a logic product, input transition time (TinTRAN) of the respective logic cells, output capacitance (CL) of the respective logic cells, and output parameters including the parameters of degradation calculation of hot carriers of the respective logic cells, which are obtained by performing a circuit simulation using the transition time of input signal and capacitance attached to the output as input parameters.
In the computer-readable storage medium, the degradation D due to time dependence of the propagation delay of the respective logic cells has, as the first output parameters, Ac and n for which D=xcex94tp/tp0=Acxc3x97tn is established where the elapse time is t, the fresh delay quantity is tp0, and the aged delay quantity is xcex94tp, and Ac depends on the circuit configuration and a bias voltage which the logic cells receive, and the n is a slope of time dependence, which is a parameter dependent on the circuit configuration and a bias voltage that the logic cells receive.
In addition, the degradation D due to the time dependence of propagation delay of the respective logic cells has, as the second output parameters, xcex2 and n for which log(D)=log(Bc)+nlog(Dtft), or log(D)=xcex2+nlog(Dtft) or LogD=log(D)=xcex2+nLogF+nLogt+nLogDt, LogDt=log(Dt) in which a frequency is established when D=Acxc3x97(Dtxc3x97f/f0xc3x97t)n=Bc(Dtxc3x97fxc3x97t)n, Bc=Ac/f0n, f0=Ac and n are extracted, and the logarithm of both sides is taken, wherein the duty is Dt and frequency is f. The LogF is the logarithm of the frequency f, and Logt is the logarithm of the time t.
The above-described first and second output parameters further include propagation delay (TpRISE) when the output signal of respective logic cells rises, and propagation delay (TpFALL) when the output signal of respective logic cells falls, and further include a transition time (ToutRISE) when the output signal of respective logic cells rises, and a transition time (ToutFALL) when the output signal of respective logic cells falls, wherein these parameters are created in the form of a table.
Also, a method for designing the first semiconductor integrated circuit device according to the invention includes the steps of creating, when designing a logic product by a combination of various types of logic cells, a transition time (TinTRAN) of the input signal of the respective logic cells and an output capacitance (CL); a transition time (ToutRISE) when an output signal rises, and a transition time (ToutFALL) when an output signal falls, which are obtained as output parameters by performance of a circuit simulation by using the transition time of input signal and output capacitance as input parameters; propagation delay (TpRISE) when the output signal rises and propagation delay (TpFALL) when the output signal falls; and delay libraries in which parameters (Ac and n or xcex2 and n) for degradation calculations of hot carriers; preparing a reference delay file by calculating propagation delays with respect to all the logic cells that constitute a logic product based on the library; and obtaining the overall propagation delays of the critical path in the logic product on the basis of the reference delay file as values of the propagation delays of the respective cells.
The method for designing the first semiconductor integrated circuit device further includes the steps of adding parameters of changes in temperature and changes in the power supply voltage to the delay libraries, and processing the parameters as an overall constant that does not require separate extraction thereof with respect to the respective logic cells and load conditions.
A method for designing the second semiconductor integrated circuit device according to the invention includes the steps of obtaining a reliability factory (RF) in the respective logic cells that constitute a logic product and reducing the reliability factor (RF) with respect to the logic cells having the reliability factor exceeding the necessity so that the reliability factor (RF) lies in a certain margin between the maximum reliability factor (RFup) and the minimum reliability factor (RFmin).
The method for designing the second semiconductor integrated circuit device further includes the step of increasing the reliability factor (RF) with respect to a logic cell, which does not meet the reliability requirement, of the respective logic cells so that it lies in a certain margin between the predetermined maximum reliability factor (RFup) and minimum reliability factor (RFmin).
The method for designing the second semiconductor integrated circuit device is featured in that, where the fresh delay quantity is tp0 and the aged delay quantity is xcex94tp, the reliability factor (RF) is expressed in terms of RF=1/(sensitivity/degradation), degradation=xcex94tp/tp0 of the respective logic cells, sensitivity(xcex94tp/tp0 of the critical path of a logic product)/(xcex94tp/tp0 of the respective logic cells).
The reliability factor can be varied by changing the transition time of the input signals of the respective logic cells. Where the transition time of the input signals is changed, (1) the current drive of the preceding cell is changed, and (2) the capacitive load of an intervening part between the preceding cell and the present cell is changed by (a) changing the resistance load (RLin) at the input side and capacitive load (CLin) at the input side by varying the channel of the intervening part, and (b) adding/inserting or removing a buffer (Buf) between the preceding cell and present cell.
Further, the reliability factor can be varied by changing the transition time of the output signal of the respective logic cells, and the transition time of output signal is changed by (1) changing the current drive of the present cell, and (2) changing the capacitive load of an intervening part between the present cell and subsequent cell by varying (a) the resistance load (RLout) and capacitive load (CLout) of the intervening part between the present cell and subsequent cell or (b) adding/inserting or removing a buffer (Buf) between the present cell and subsequent cell.
In addition, the maximum reliability factor (RFup) and minimum reliability factor (RFmin) are set, depending on the circuit operation time and degradation allowance of a logic product.